3D integrated circuits contain stacked chips that are electrically connected to one another by chip TSVs that extend vertically through the silicon wafers of the chips. Common chip TSV configurations are shown in FIGS. 1A and 1B (PRIOR ART). In order to establish an electrical connection between chips, the chip TSV contains an electrically conducting material, such as a metal, particularly copper (Cu). This material sometimes extrudes from the via during manufacturing or operation of the 3D integrated circuit, causing damage to structures near the chip TSV as shown in FIG. 1C (PRIOR ART) or cracking of an oxide film that forms on top of the chip TSV as shown in FIG. 1D (PRIOR ART). Both of these effects are detrimental to the 3D integrated circuit and may cause the entire circuit to fail.
Prior to the present invention, causes of via extrusion were poorly understood and effective ways of reducing via extrusion have not been demonstrated.